Power consumption is important in double-data rate data buffer chips and registered clock driver chips. A challenge in the chip designs is to reduce power consumption for continuous time linear equalizers and following circuits that receive signal frequencies of one giga-Hertz and higher. Conventional continuous time linear equalizers designs currently include active designs and passive RC-based designs. Conventional active designs are essentially an amplifier with a source degenerator and a bandpass filter frequency response. However, the conventional active designs burn more power as signal speeds increase. The conventional designs also incur power consumption from summing digital-to-analog circuitry at an output node. Conventional passive designs achieve lower power consumption than the active designs. However, the resistor process variation is about ±20% causing the filter response to drift. The drifts make the circuits hard to calibrate.
It would be desirable to implement series continuous time linear equalizers